The present invention relates in general to flipflop circuits and, more particularly, to a circuit and method of resetting a master/slave flipflop.
Master/slave flipflops are commonly used in electronic circuit design to latch a data input signal at an output in response to a clock signal so that transitions of the data output signal of the flipflop are synchronized to the clock signal. A master/slave type flipflop is responsive to opposite phases of the clock signal whereby the data input signal is latched internally in the master portion of the flipflop during one phase of the clock signal followed by a transfer of the data through the slave portion to the output of flipflop at the opposite phase of the clock signal.
An important feature of the master/slave flipflop is the reset option whereby a reset signal can set the output of the flipflop to a known state, for example, during initialization of the system. Therefore, a need exists for a circuit and method of resetting a master/slave flipflop.